1. Field of the Invention
The invention relates to a semiconductor memory device in which data read timing is determined by operation of replica bit lines. The invention further relates to a control method for the semiconductor memory device.
2. Description of Related Art
FIG. 8 shows a portion of a conventional read-only memory (“ROM”) circuit 100 using replica bit lines. The ROM circuit 100 has regular bit lines BL, regular data lines DL, replica bit lines RBL, and replica data lines RDL. Replica memory cells RC1 to RCn (n=natural number) are connected to each of the replica bit lines RBL, and memory cells C1 to Cn are connected to each of the regular bit lines BL. The source of a memory cell transistor BM1 of the memory cell C1 is connected to a ground voltage VSS, in which data “0” is retained. The sources of memory cell transistors BM2 and BMn of the memory cells C2 and Cn are set to a floating state, in which data “1” is retained. The sources of replica memory cell transistors RM1 to RMn of the replica memory cells RC1 to RCn are all coupled to the ground voltage VSS.
By reference to a timing diagram shown in FIG. 9, operation of the ROM circuit 100 will be described hereinafter. In a time period P1, the memory cell C1 retaining data “0” is selected. Upon completion of precharging (at time T11), the replica bit line RBL and the regular bit line BL are charged to a first precharge voltage value PV1 indicative of data “0”. In addition, a replica data line RDL and a regular data line DL are charged to the level of a power source voltage VCC. Upon completion of the precharging (after the time T11), the voltage value on the replica data line RDL and the regular data line DL begins to drop. Then, when the replica data line RDL has dropped to the level of a predetermined voltage value, a latch control signal LCS is transmitted (arrow YY11). With the latch control signal LCS being used as a trigger, data flowing on the regular data line DL is latched in a latch section 103 (arrow YY12). In this case, the voltage value on the regular data line DL is low, so that data “0” is latched.
On the other hand, in a period P2, the memory cell C2 retaining data “1” is selected. Upon completion of precharging (at time T21), the regular bit line BL is precharged to a second precharge voltage value PV2 (higher than the first precharge voltage value PV1) that is indicative of data “1”. Then, upon completion of the precharging (after the time T21), the voltage value of the replica data line RDL begins to drop; however, the voltage value of the regular data line DL does not begin to drop. Then, a latch control signal LCS is transmitted (arrow YY21), data flowing on the regular data line DL is latched with the latch control signal LCS being used as a trigger (arrow YY22). In this case, the voltage value of the regular data line DL is not decreased low, so that data “1” is latched.
Thus, using the replica bit line RBL, the readout of data “0” is thus performed for each communication, and the latch control signal LCS (signal to control a latch circuit for bit line readout data) is transmitted from a latch control circuit 102 with the readout completion timing (time T12, T22). Then, in the latch section 103, the data on the regular data line DL is latched in response to the latch control signal LCS and is output. That is, the replica data line RDL has the functionality of determining the timing of latching the data on the regular data line DL into latch section 103 by performing the readout of data “0” for each communication. Other examples of semiconductor memory devices using replica bit lines are disclosed in Japanese Unexamined Patent Application Publication No. 03-141876.